Multi-corner multi-mode (MCMM) analysis is a technique intended to provide high confidence results for timing and other metrics without performing exhaustive simulation of all possible IC conditions. The analysis uses multiple design points to examine the effects of process and environmental variations as well as changes caused by shifts into different operating modes.
Multi-corner analysis is intended to capture the effects of variation on the manufacturing process as well as voltage and temperature. Multi-mode analysis alongside has become more commonplace because of the demand for ICs that have different low-power modes, as well as test modes and various functional modes.
Sudhakar Jilla’s 2007 article for TDF, “Using multi-corner, multi-mode techniques”, outlined the key problem for designers: “As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a implementation system that can handle multiple mode/corners scenarios simultaneously, the design team has to implement the design for a chosen worst corner, set some margins/pessimism, and then hope that the chip works at other mode/corners.”
However, designers have found that the worst corner is not always easy to predict. For example, as high-Vt, low-leakage cells get colder they do not speed up in the way that circuits built around faster low-Vt transistors do. They can start to slow down, a phenomenon that’s earned the name “temperature inversion dependence”, a problem first described by Vassilios Gerousis of Infineon Technologies at the 2003 IEEE Custom Integrated Circuits Conference. As a result, intelligent timing analysis is required to provide high-quality MCMM results.
The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]
Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
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