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January 7, 2015
A holistic approach to IoT chip design
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
Expert Insight | Topics:
Embedded - Architecture & Design
,
IP - Assembly & Integration
| Tags:
co-optimization
,
low-power design
,
multi-Vt design
,
smart analog
| Organizations:
Synopsys
March 28, 2012
FD-SOI
Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
Guide | Topics:
EDA - DFM
,
IC Implementation
| Tags:
body bias
,
bonded wafer
,
FD-SOI
,
multi-Vt design
,
partially depleted SOI
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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