How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
How to design with finFETs, including the impact on standard cells, IP, SRAM; the effects of fin quantization; extraction and parasitics; AMS issues and more.
Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Meeting the challenges of moving beyond planar integration to side by side, and eventually truly stacked, dice, for designers, tool vendors and the supply chain.
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