IC Implementation

October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
October 9, 2012

Physical verification of 20nm designs through integrated double-patterning analysis and repair

Finding and fixing double patterning problems in 20nm designs
Article  |  Tags: , ,   |  Organizations:
September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
May 23, 2012

VHDL

VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
Guide  |  Tags: , , , , ,
May 21, 2012

Modelling envelope-tracking RF PAs for LTE at high dynamic range

Current techniques for modelling RF power amplifiers don't provide the dynamic range necessary to simulate their performance properly when used in the energy-saving envelope-tracking mode necessary to give LTE terminals a decent battery life.
March 28, 2012

FinFETs

It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?
March 28, 2012

FD-SOI

Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
January 16, 2012

Unified Power Format (UPF)

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
Article  |  Tags: , , , , ,   |  Organizations: ,
June 3, 2011

This one now goes to 12

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.
Article  |  Tags:   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors