IC Implementation

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]

A bid for more interactivity is one of the program cornerstones for the 48th Design Automation Conference.

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.

DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.

The article reviews the design assessment process that a company should undertake when developing an analog-centric application-specific integrated circuit (ASIC). The authors argue that a number of myths surround strategies that incorporate a large amount of specialist analog design work, including evaluations related to cost and functionality. In particular, the need for differentiation in today's [...]

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.