IC Implementation

January 16, 2012

Unified Power Format (UPF)

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
August 23, 2011

Parting of the ways

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.
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June 3, 2011

This one now goes to 12

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.
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June 1, 2011

The challenge of analog, mixed-signal and custom physical implementation at 28nm

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
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June 1, 2011

Opening up the dialogue

A bid for more interactivity is one of the program cornerstones for the 48th Design Automation Conference.
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June 1, 2011

The new semiconductor ecosystem: wants and needs

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
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February 25, 2011

The fast run

DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.
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February 25, 2011

Demystifying analog and mixed-signal ASICs

The article reviews the design assessment process that a company should undertake when developing an analog-centric application-specific integrated circuit (ASIC). The authors argue that a number of myths surround strategies that incorporate a large amount of specialist analog design work, including evaluations related to cost and functionality. In particular, the need for differentiation in today's [...]
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December 14, 2010

Characterizing PLL jitter from power supply fluctuations using mixed-signal simulations

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]
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June 1, 2010

A matter of timing

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
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