Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
design for security
Arm looks to explore new realms for security with v9
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Accellera IP security group expects standard by year end
The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
IP partnership aims to crack down on physical hacks
UltraSoC and Agile Analog have teamed up to build an infrastructure that can help guard against physical attacks on SoCs.
Feed fake news to hardware hackers
Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
Accellera adds detail to proposed security assurance model
Accellera's security assurance working group has set out some of its plans in a white paper.
Microsoft Azure aims to get inside SoCs with cloud security plan
Microsoft Azure aims to use royalty-free IP to build a more secure IoT and extend the reach of its cloud services.
The unknown unknowns of secure devices
Developing a security assurance standard for IP faces numerous problems but Accellera working-group members are trying to find an answer.
Security, machine learning, and variety at DAC
Security and machine learning are two topics that take center stage at DAC this year, says the conference’s general chair Rob Aitken.