3D-IC

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.