Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
DAC 2018 preview: Baum
Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
DAC 2018 preview: Synopsys
DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.
DAC 2018 preview: Verific
The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Switch to orbit mode boosts MRAM on 300mm wafers
Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
Accellera signs off on SystemC control standard
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
Synopsys speeds PrimeTime with AI
Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
Case study demonstrates 59% extra power savings for HPC
Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24×24 array HPC chip in detail
Pillar transistor points to smaller SRAMs at 5nm
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Arm Cortex-A processor team focuses on formal
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.