Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
November 30, 2018

Design Compiler updated for 5nm and beyond

Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.

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November 27, 2018

Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results

Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry’s golden sign-off tools.

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November 15, 2018

Xpedition updated for schematic verification and DFT

Mentor’s flagship PCB suite is aiming to offer another ‘shift left’ in verification as respins rise.

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November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.

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November 13, 2018

Accellera updates UVM reference implementation

Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.

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November 7, 2018

Symphony raises crescendo for AMS simulation

Mentor’s updated AMS platform claims performance boost by obviating ‘legacy’ technology.

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November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.

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October 31, 2018

Cadence adds deep-learning support to audio DSP

Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.

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October 29, 2018

Mentor extends Tessent for debug and automotive pattern generation

As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.

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October 22, 2018

IEDM to examine scaling from multiple directions

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.

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