Design Compiler updated for 5nm and beyond
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry’s golden sign-off tools.
Mentor’s flagship PCB suite is aiming to offer another ‘shift left’ in verification as respins rise.
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
Mentor’s updated AMS platform claims performance boost by obviating ‘legacy’ technology.
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.