IPSoC: Software power optimization ‘must start earlier’
Embedded software engineers need to focus on power optimization in their code much earlier and more comprehensively than many of them do today, says Mentor Graphics technologist Colin Walls.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
IPSoC: Configurability and the rise of the IP factory
Traditional IP reuse is giving way to configurable, customized cores delivered by semi-automated “IP factory” groups.
IPSoC: 20nm causes analog ‘density fill headaches’
20nm design is fraught with problems for analog design but one that causes the biggest headaches is density variation, says Synopsys’ Joachim Kunkel.
IPSoC: Tabula aims for 22nm white-label parts
Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an ‘app store’ for data-center hardware.
FinFET tipsheet for IEDM
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Cadence gears up for automotive switch to ethernet
Cadence Design Systems has developed semiconductor IP for the automotive industry’s OPEN Alliance to make ethernet the core networking backbone of future motor vehicles.
Graphics provide the push for NI’s readymades plan
National Instruments wants to shift the focus for many embedded systems designers away from hardware cost optimization towards graphical programming as a way of reducing the time it takes to get targets up, running and productive.
‘Process and metrics before tools for better verification’
Chip-design teams are running into problems with verification because they are focused too much on tools and not enough on processes, Mentor Graphics chief scientist Harry Foster explained today at the first of a series of Verification Futures seminars hosted by TVS in Europe this week.
IJTAG: delivering an industry platform for IP test and integration
Mentor’s Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
3DIC – the advantages and the challenges of vertical integration
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore’s Law.