25 million gate prototyper arrives through collaboration
A team effort between three French companies has resulted in the launch of an FPGA prototyping system that is intended to provide emulation of designs with up to 25 million ASIC gates.
Author Archives: Chris Edwards
Cadence buys IP provider Cosmic
Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
GlobalFoundries inks IP deals
GlobalFoundries has signed deals to let the foundry offer power-saving clocks, a massively parallel floating-point processor and interface IP from Rambus. They are "uncommon solutions" to come from a foundry, the company claims.
GlobalFoundries and Samsung talk finFET progress at CPTF
GlobalFoundries and Samsung described how they are readying finFETs for production at CPTF 2013 and how the 28nm processes will have a long shelf life.
Cadence updates Virtuoso for the 20nm generation
Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
Future Horizons: prepare for a tight 2014
Even though inventories are slack right, chipmakers could be struggling to find wafers in 2014.
The silicon industry’s crunch time
Future Horizon’s forecast meeting for the first half of 2013 made it clear how the electronics sector and the semiconductor industry in particular is facing big problems.
Samsung lines up tool providers for finFET tapeouts
14nm finFET test-chip designs are moving through Samsung's fab as ARM, Cadence Design Systems and Synopsys continue to check their flows on the new process.
DATE conference prepares program for March
In 2013, the Design Automation and Test in Europe (DATE) conference returns to Grenoble, France and with focus days on the Internet of Things and the cloud.
Altera and ARM unite FPGA and processor debug
Altera has cut a deal with ARM to bring unified debug support to the FPGA fabric and Cortex-A9 processors inside the Cyclone SoC products, using a specialized version of ARM’s DS5 tool.