Performance and timeout checks added to on-chip network
Sonics has add static performance analysis to its SonicsStudio tool and timeout detection to its SonicsGN network intended to prevent SoCs locking up.
Author Archives: Chris Edwards
Cadence shifts emulation to the data center
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
UltraSoC adds CoreSight and Ceva debug support
UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
ARM ports Trustzone down to Cortex-M
ARM is bringing the Trustzone security architecture to future Cortex-M processor cores, combining that with a version of AHB that will recognise the difference between secure and non-secure transactions.
Wind River aims for cloud revenue in IoT strategy
Wind River aims to change its business model to collect money from cloud services for IoT instead of selling licences for embedded devices.
ARM targets cache-coherent GPU computing with CoreLink addition
ARM has developed a version of its CoreLink on-chip interconnect IP intended to support systems based on its big.Little processors combinations that need a cache-coherent GPU connection with lower latency and higher peak throughput.
Ceva builds DSP chip and board for IoT prototyping
IP supplier CEVA has made a development platform intended to speed up the prototyping of IoT and similar devices based on its TeakLite-4 DSP core.
ARM snaps up Carbon model IP for prototyping
ARM has moved back into system-level modelling with the decision to buy the tools and models developed by Carbon Design Systems
IMEC 5nm test chip to explore EUV and SAQP litho options
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Expanding role of UVM takes center stage at DVCon Europe
Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.