DFT

February 25, 2011

Innovations at ITC 2010

Poster sessions are all too often given Cinderella status at major conferences, but they often contain novel and interesting responses to current technology challenges. This article reviews five poster papers that were released at the 2010 International Test Conference ranging in topic from improved device interfaces for gigahertz test to IP security to the diagnosing [...]
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December 14, 2010

Achieving teraflops performance with 28nm FPGAs

FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
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June 1, 2010

Energy debugging – the next step in MCU software optimization

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.
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April 14, 2010

The new kid on the USBlock: introducing SuperSpeed 3.0

The USB 3.0 specification was approved in 2008 and the first certified products to take advantage of its SuperSpeed (5Gbit/s) were launched at January’s Consumer Electronics Show in Las Vegas. As more support for the standard becomes available, engineers will find themselves considering the specification’s implementation on all types of system projects during the course [...]
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December 1, 2009

Silicon test moves up the food chain

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

September 1, 2009

Ensuring reliability through design separation

System designs have traditionally achieved reliability through redundancy, even though this inevitably increases component count, logic size, system power and cost. The article describes the design separation feature in Altera software that seeks to address these as well as today’s conflicting needs for low power, small size and high functionality while maintaining high reliability and […]

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September 1, 2009

Pushing USB 2.0 to the limit

USB offers many advantages for use on embedded systems, although software developers remain concerned about the additional complexity it can bring to an application. For example, software drivers for SPI, RS-232 and other traditional serial protocols typically involve little more than read and write routines, while USB software drivers can span thousands of lines, incorporating […]

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June 1, 2009

Antenna design considerations

An overview of antenna design considerations is presented. These considerations include system requirements, antenna selection, antenna placement, antenna element design/simulation and antenna measurements. A center-fed dipole antenna is presented as a design/simulation example. A measurement discussion includes reflection parameter measurements and directive gain measurements. Antenna requirements Gain and communication range With the advent of prolific […]

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December 1, 2008

OCP performance monitoring with programmable instruments

The process of proving the system is working and performing optimally, under all application and environmental conditions, has become too inefficient and difficult for existing methodologies. Traditional methods for addressing post-silicon requirements have reached the point of diminishing returns. What was once an exercise of designing, implementing and verifying 25,000 to 50,000 gates of instrumentation […]

December 1, 2008

IP hardens up again

Richard Goering System-on-chip designers who work with third-party silicon intellectual property (IP) will see some significant changes at 32nm and below. Physical IP will be highly optimized to specific processes, following intense collaborations between large IP providers and foundries. Processor IP may become less synthesizable and make more use of hard macros. On the plus […]

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