IJTAG: delivering an industry platform for IP test and integration

Steve Pateras is product marketing director within Mentor Graphics Silicon Test Solutions group and has responsibility for the company’s ATPG and DFT products. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada.

Integrating and testing IP blocks in large SoCs is typically a time consuming, manual effort. The IEEE proposed standard P1687 (‘IJTAG’) aims to solve this problem.

IJTAG lets IP providers and SoC integrators replace ad hoc and custom solutions with IP plug-and-play integration. There is even software available to automate the connection of any number of IJTAG-compliant IP blocks into an integrated, hierarchical network accessed from a single point.

IJTAG saves engineering time and significantly reduces the length of an aggregated test sequence for all the IP blocks in an SoC. This translates directly into reduced test time and smaller tester memory requirements.

Challenges in IP integration and test

Today’s SoCs can contain hundreds of different, reusable blocks of IP (Figure 1). These are pre-defined blocks of analog, digital, or mixed-signal circuitry performing particular functions. Examples include clock generators, interfaces to external measurement probes, radio tuners, analog signal converters, and digital signal processors. There are hundreds more. Some are designed and maintained in-house; others come from third-party providers.

There are de-facto standards for what information must be included in the library package delivered with an IP block. Unfortunately, it frequently does not include protocols for communicating test features or other commands to the block. Nor often is there any predefined way of integrating specific test features into the overall design. Some IPs, like embedded processors and SerDes I/O interfaces, may come with built-in self-test (BIST) circuitry. But hardly any off-the-shelf IP includes a complete, ready-to-go test or debug solution.

Moreover, there has not been a common protocol to interface to these blocks, so a design team must acquire additional learning and customization to communicate to it.

Consequently, integration with, testing of, and communication to IP blocks used in large-scale semiconductor devices have generally entailed considerable manual effort. This can lead to frequent design changes and delays. Test engineers are often unfamiliar with the blocks. Those blocks are themselves increasing in number and diversity. There are complicated operational and test setup sequences to manage.

The IJTAG Solution

The IEEE P1687 committee came up with the proposed IJTAG standard to address these integration and test challenges. It builds on the popular IEEE 1149.1 (JTAG) standard for board and card-level test access.

IJTAG provides a set of uniform methods to describe and access IP blocks inside a chip, creating a basis for design, test, and system engineers to easily reuse IP. The standard offers a path to plug-and-play IP integration by enabling communication to all instruments (IP blocks) from a single test access point.

IJTAG is being defined by a broad coalition that includes IP vendors, IP users, major ATE companies, and the three largest EDA vendors. With this breadth of support, the expectation is that it will be rapidly and widely adopted by the industry. There is already commercial support for the automated implementation of IJTAG in large, complex designs.

A technical description of IJTAG can be found in this article.

As illustrated in Figure 2, IJTAG describes an embedded instrument’s ports and registers as well as its control and access sequences through two new languages. These are the Instrument Connectivity Language (ICL), and the Procedural Description Language (PDL).

• ICL provides an abstract, hierarchical definition of how to access and control the instrument, and describes the network connecting all the different instruments.
• PDL describes how to operate and monitor the instrument.

IJTAG automation

With an ICL and PDL description of an instrument and its operations, the instrument can be easily ported between designs. The descriptions can be ‘retargeted’ from the instrument level to the top level of the design. To fully enable and automate the use of IJTAG, a tool such as Mentor Graphics’ Tessent IJTAG can read in, verify, retarget those descriptions. It then writes out a Verilog test bench language and standard test vector formats (Figure 3).

Overall, IJTAG-based automation provides good improvements in ease of use, as well as quality and correctness, compared to manual methods.

The business case for IJTAG

Two driving forces in our industry are cost reduction and increased functionality in smaller packages. One way to accomplish these goals is to concentrate in-house development efforts on the functionality that differentiates a product. You then add commodity functionality (e.g., embedded CPUs, SerDes , USB, WiFi, PLLs, sensors, power/clock controllers etc.) from in-house IP databases or third-parties.

Because little of the off-the-shelf IP contains standards for test access, companies have developed custom systems and flows to manage in-house IP test. These typically use proprietary formats to describe the IP and the test patterns that come with it. These custom solutions can be replaced by IJTAG-based versions with little effort. Users then gain the significant advantages of moving to an open standard. These include greater efficiency and scalability, as well as elimination of the need to devote internal resources to maintaining a custom strategy.

Summary

The growth in SoC functionality and performance has led to the increased use of diverse sets of reusable IP. Current integration and test of these blocks are messy endeavors. Increasingly, companies are adopting the IJTAG-based integration flow to improve the test and debug of all the IP in their designs. Adoption is easy and cost-effective, and automation techniques already exist to facilitate IJTAG-based systems.

IJTAG should quickly become the dominant standard for plug-and-play integration of IP instrumentation, including control of boundary scan, built-in self-test (BIST), internal scan chains, and debug and monitoring features in IP blocks. The standard promises to substantially reduce the time and effort required to assemble large SoC designs from reusable IP blocks.