DFT

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.