Synopsys

July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
July 19, 2013
Cisco switch chip layout detail

Eliminating iterations in gigahertz ASIC handoff

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
May 23, 2013
Cost of verification

Facing the verification management challenge

The growing verification challenge, and how to address it by coordinating multiple debug strategies.
April 24, 2013
Mick Posner, Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Expert Insight  |  Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,
April 17, 2013
Xilinx 3D-IC interposer featured image

3D-IC integration – a stepwise approach

2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
Article  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
April 10, 2013
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
Expert Insight  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , ,   |  Organizations:
April 4, 2013
Michael Sanie, Synopsys

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
February 12, 2013
Nithya Ruff, Director of Product Marketing for Virtual Prototyping Solutions at Synopsys.

Dev kits bring virtual prototyping to everyone

Now companies in any tier can use development kits as a platform to speed development, bridge the hardware-software divide and build out ecosystems quickly.
Expert Insight  |  Topics: Embedded - Architecture & Design  |  Tags: ,   |  Organizations:
February 12, 2013
tdf-altvp-feb13-featim

How virtual prototyping enabled Altera’s SoC FPGAs

The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
Article  |  Topics: Embedded - Architecture & Design, - Embedded Topics  |  Tags: , ,   |  Organizations: ,
February 5, 2013
tdf-snps-ARMcc-feb13-featim

Using VIP for cache coherency hardware implementations

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,

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