Synopsys

September 16, 2013

USB 3.0 protocol layer – part 2

A look at the role of four types of transaction in the USB 3.0 protocol layer: bulk, control, interrupt and isochronous.
Article  |  Topics: IP - Assembly & Integration  |  Tags: , ,   |  Organizations:
September 16, 2013

The USB 3.0 Physical Layer

A look at the USB 3.0 physical layer, including the PHY and the physical connection between two ports, which is carried on two differential data pairs.
Article  |  Topics: IP - Assembly & Integration  |  Tags: ,   |  Organizations:
September 10, 2013
embeddebug_feat img

Debugging with virtual prototypes – Part One

The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: ,   |  Organizations: , , ,
September 3, 2013
SNPS TDF UPF hierarchy feat img

Choosing a block representation in a UPF-based hierarchical multi-voltage IC design

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations:
August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
August 12, 2013
Steve Smith of Synopsys

Help Wanted? Help Given! 3D-IC design is ready for take-off

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
July 19, 2013
Cisco switch chip layout detail

Eliminating iterations in gigahertz ASIC handoff

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
May 23, 2013
Cost of verification

Facing the verification management challenge

The growing verification challenge, and how to address it by coordinating multiple debug strategies.
April 24, 2013
Mick Posner, Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Expert Insight  |  Topics: IP - Assembly & Integration, - EDA Topics, IP Topics, EDA - Verification  |  Tags: , ,   |  Organizations: ,

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