Synopsys

August 4, 2015
Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

Building better debug facilities for bigger FPGA-based prototypes

The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations: ,
June 22, 2015

Verifying MIPI interfaces in SoCs

Verifying MIPI interfaces including CSI-2, CPHY, DPHY, MPY, Unipro and the UFS host controller on complex SoCs - should you make or buy the necessary VIP?
Article  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , , , , ,   |  Organizations: ,
June 17, 2015
Joe Mallett is senior manager, product marketing for FPGA-based synthesis software tools at Synopsys.

Eight tips for choosing your next FPGA tool

Eight issues to consider when choosing an FPGA tool, including risk minimisation, routing issues, ability to iterate, IP freedom and more
Expert Insight  |  Topics: EDA Topics  |  Tags: , ,   |  Organizations:
May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
April 30, 2015
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

Putting emulation on the map

Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , ,   |  Organizations: , ,
April 20, 2015

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
April 3, 2015
Early and accurate power estimation - feat img

A better method for early and accurate power estimation

Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
February 27, 2015

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Article  |  Topics: IP - Assembly & Integration, Design Management  |  Tags: , , , , ,   |  Organizations:
February 3, 2015
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Automotive ICs drive advanced design at established nodes

Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.
Expert Insight  |  Topics: EDA - IC Implementation  |  Tags: , ,   |  Organizations:
January 30, 2015

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,

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