Synopsys

This article looks at the way in which various representations of a block of a design have different implications in a UPF based power-aware hierarchical design flow.

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis

The growing verification challenge, and how to address it by coordinating multiple debug strategies.

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.

2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.