January 7, 2015
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
December 8, 2014
CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs
December 1, 2014
Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues
November 6, 2014
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 31, 2014
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
October 27, 2014
This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market
October 15, 2014
A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes
October 10, 2014
FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
September 18, 2014
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
September 2, 2014
How EDA tools are evolving to make it possible to design with finFET processes.