Using a physically aware flow to ensure that fixing one ECO doesn’t introduce another during sign off.
The increasing density and operating speeds characteristic of today’s ICs make it challenging to lay out a chip, route signals through it, and then ensure the resulting design meets the required timing constraints. The challenge is compounded because today’s ICs must meet timing for many more operating scenarios than previous generations of chips.
One way to make timing signoff faster is to ensure that any engineering change orders (fixes, or ECOs) are fulfilled using a predictable flow that is placement and routing-aware and eliminates timing violations in all signoff scenarios, without introducing new ones. Implementation tools, supported by static timing analysis, can be used in a signoff flow to tackle issues such as:
- fixing design rule constraint (DRC), setup, and hold violations, without introducing new ones
- reducing timing pessimism, using techniques such as advanced on-chip variation (AOCV), parametric on-chip variation (POCV), and path-based analysis (PBA), across all scenarios
- using physical design information to achieve the best quality of results for ECOs, without introducing major changes into designs that are already placed and routed.
It is important than any such flow can fix very complex designs quickly enough that design teams can find and repair numerous violations within a reasonable amount of time.
Timing closure requires a signoff-driven approach
Implementation tools use timing-driven algorithms for placement, clock tree synthesis, and routing. They share timing engines with signoff timing tools to ensure correlation between the physical design and the signoff timing results. Despite this correlation, timing violations can still arise after place and route for a number of reasons:
- The place and route process may have been undertaken without knowledge of all the constraints for all the scenarios. Timing analysis using the full set of constraints for all scenarios can then reveal new violations during signoff.
- IP design teams sometimes over-constrain selected blocks to ensure their operation at higher frequencies than required for the current design. While this approach enables reuse in other chips, it can lead to timing constraint differences between the implementation and signoff tools.
When violations appear during signoff, design teams need a methodology that closes timing violations quickly and efficiently, as shown in Figure 1.
Figure 1 Signoff-driven timing closure approach (Source: Synopsys)
A signoff-driven approach to timing closure first optimizes the design using timing driven optimization of the physical implementation of critical scenarios, since the implementation tools have the most powerful optimization and transformation techniques. Signoff-accurate, physically aware, all-scenario timing analysis is then used to guide the final-stage ECOs undertaken by the place-and-route tools.
ECO solutions based on timing snapshots are inadequate for advanced designs
Some design teams use ECO-specific tools that read in a snapshot of the signoff timing data, and then suggest fixes based on a simple estimation. These are inadequate for addressing designs with millions of instances and numerous scenarios. Such tools are also unable to properly estimate the impact of issues such as signal integrity, PBA, waveform propagation, AOCV, or POCV on timing.
As a result, ECO solutions that rely on timing estimations, or which don’t use signoff timing engines, are less predictable, which can lead to additional iterations to close timing.
Signoff-driven timing closure ECO flow in the Synopsys Galaxy Platform
The Synopsys Galaxy Platform ECO flow using IC Compiler, StarRC, and PrimeTime is shown here.
Figure 2 Signoff-driven timing closure ECO in the Synopsys Galaxy Platform (Source: Synopsys)
IC Compiler is a physical implementation tool that includes design planning, placement, clock synthesis, and routing facilities, and which supports concurrent multi-corner, multi-mode optimization.
The PrimeTime ECO guidance architecture uses accurate parasitics extracted by StarRC to create an ASCII format, Tcl-based change file for IC Compiler, which is optimized with physical location information to ensure that the fixes it suggests can be implemented.
The guidance architecture uses three key technologies:
The ECO timing graph captures all related parts of the design, including violating endpoints and the slack values for these points. This compact graph is created quickly and efficiently for each scenario.
Violations are prioritized based on the relative criticality of the graph segments, each of which represents a ‘per stage’ slack value.
The composite graph view is created from the individual timing graphs and provides a global view of all violations across all scenarios. The ECO algorithms use this composite graph view to ensure that fixing an issue for one scenario will not create an issue for another (see figure 3).
Figure 3 A composite timing graph encompasses all scenarios (Source: Synopsys)
Figure 3 A composite timing graph encompasses all scenarios (Source: Synopsys)
Calibrated estimation evaluates all the different ways to fix a given timing violation and estimates the outcome for each approach, without requiring a full timing analysis. It then calibrates the results with the signoff-accurate timing data from the ‘all-scenario’ timing view, accounting for all analysis techniques including signal integrity, waveform propagation, and AOCV. This approach is quicker than a full timing analysis and improves the turnaround time per cell operation. It should also lead to highly predictable results with fewer changes to the netlist.
Physically aware technology reduces ECO iterations
The way a design has been placed and routed often presents opportunities to fix issues with minimal impact to the layout.
A new PrimeTime ECO technology uses a lightweight physical interface that can populate the composite timing graph with physical information. PrimeTime ECO can then consider placement congestion and blockages and provide precise ECO guidance, enhanced with location information. Accurate ECO timing estimation can also be achieved by separating the original net parasitics, based on the target location, and recalculating cell and net delays, as well as crosstalk effects. This ensures more predictable signoff timing closure after implementation.
PrimeTime ECO can consider the whole net route, rather than just the area around a driver or load pin, to find a space to insert a buffer. This increases IC Compiler’s chances of implementing an ECO fix in congested regions, and is the best way to fix DRC violations caused by long or high-fanout nets.
Figure 4 shows two examples of placement-aware ECO. In the first, the technique prevents cell displacement by constraining cell upsizing to the available neighboring free space; in the second, it recognizes placement blockage and inserts an ECO buffer on route.
Figure 4 How placement-aware ECO fixes issues without creating new ones (Source: Synopsys)
Figure 5 shows examples where routing-aware ECO can improve the fix rate and quality of results for maximum transition violations by inserting buffers where they best fit in the route topology.
Figure 5 Improved fix rate with routing-aware ECO (Source: Synopsys)
For the most challenging timing violations, in which space is not available around the target pins or along the route, PrimeTime generates ECO guidance that tells the implementation tool where the lowest placement density is along a path. During the process of checking that the ECO implementation meets all the design rules (‘legalization’), IC Compiler can move cells in this area to make space for the ECO changes.
Figure 6 shows the ECO flow considering placement density and fixing violations, despite limited free space.
Figure 6 Density-aware ECO can find space in highly congested regions to add buffers (Source: Synopsys)
The physically aware ECO architecture is also aware of the way in which the nets it is trying to fix are routed through different voltage domains, and tries to fix issues without introducing electrical rule violations.
Recovering power and area
The Galaxy implementation flow enables designers to apply power- and area-recovery technologies all the way from logic synthesis to post-route optimization.
On timing paths with positive timing slack, cells can be replaced with lower-power or smaller versions. Swapping cells for higher threshold voltage (Vth) versions preserves placement and routing, and can cut leakage power. Using smaller cells also makes space for other ECO fixes.
During timing closure, PrimeTime uses various pessimism-reduction technologies, including PBA, waveform propagation analysis, AOCV and POCV, to find other recovery opportunities. To ensure successful design closure, it is important to validate the ECO guidance these analyses suggest using the signoff timing engine in all scenarios before submission.
ECO implementation with minimum physical impact
Routing changes during ECO implementation can affect signoff timing due to changes in wire load or crosstalk. PrimeTime’s physically aware ECO guidance suggests ECO locations close to the target pin or original net route, and IC Compiler then restricts route changes to the local segment necessary for the newly inserted ECO cell, as shown.
Figure 7 The effect of IC Compiler’s minimum physical impact technology on ECO routing (Source: Synopsys)
By reusing most of the original net route, the changes in wire load or crosstalk effects are minimal and predictable.
PrimeTime signoff-driven ECO guidance results
The PrimeTime ECO guidance technology addresses the runtime and memory impact of an increasing number of scenarios and accelerates timing closure by minimizing the number of ECO iterations.
Resource-efficient multi-scenario ECO guidance
As the number of scenarios increases with conventional ECO tools, runtimes grow at a nearly exponential rate. With the PrimeTime ECO guidance algorithms, runtimes increase minimally with an increasing numbers of scenarios.
This is because the combination of the new timing-graph ECO views and the calibrated estimation approach enables PrimeTime ECO guidance to minimize the number of fixes it recommends to the implementation tools to meet timing in all scenarios.
PrimeTime ECO guidance runs efficiently even when the number of scenarios to be analyzed exceeds the number of processor cores available. An additional benefit of the ‘all-scenario’ view of timing violations is the ability to run with fewer cores than the number of scenarios at the same fix rate.
Predictable timing closure with physically aware technology
Physically aware ECO guidance reduces the amount the layout is changed during ECO implementation to achieve timing closure. This leads to high single-pass fix rates for DRC, setup, and hold violations.
Leakage recovery with IC Compiler and PrimeTime
The amount of leakage recovery achievable after timing closure is dependent on the power optimization efforts that have already been made during the implementation flow. If there is scope for further optimizations, PrimeTime and IC Compiler together can have a significant impact on leakage power.
New technologies in PrimeTime deliver a signoff-accurate methodology to close timing in the numerous scenarios for which designers must now achieve sign-off. The combination of PrimeTime physically aware ECO guidance and IC Compiler implementation of those ECO fixes improves the chances of a design being fixed and meeting timing in one pass.
James Chuang is a technical marketing manager at Synopsys for the PrimeTime Suite. Prior to his current role, he was a corporate applications engineer responsible for logic synthesis, static timing analysis, and ECO optimization products in the EDA industry. James received his BS degree in electronics engineering from National Chiao-Tung University in Taiwan.
Company infoSynopsys Corporate Headquarters 700 East Middlefield Road Mountain View, CA 94043 (650) 584-5000 (800) 541-7737 www.synopsys.com
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