SNUG 2012 notebook: Critical mass takes ever more collaboration

By TDF Staff |  No Comments  |  Posted: March 28, 2012
Topics/Categories: Blog Topics, Conferences, Blog - EDA  |  Tags: ,  | Organizations:

Aart de Geus, chairman and CEO of Synopsys, opened the SNUG 2012 meeting in Silicon Valley, by talking about gaining critical mass through collaboration.

He said that the effort to increase functional density causes complexity to scale, something we used to attribute to Moore’s Law. Unfortunately, moving to the next process node no longer halves the cost of a transistor as before, but saves less than that. Meanwhile the technical challenges continue to mount, and the move to the next node will only be harder.

In this environment, success is not the sum of the individual functions, but the product of many contributing factors. The next SoCs will need a systematic implementation and verification flow plus many types of IP, yet must also be differentiated from others built using the same functional blocks. Successful companies must be better, sooner, or cheaper than their competition – and keep on being so.

Companies need systematic critical mass, and lots of collaboration with partners, vendors, and the rest of the design and supply chain. Companies need to understand how and who to partner with, and need to show similar levels of commitment, competence, and the ability to compromise and find a solution that is good-enough for today. For the foreseeable future, electronics will continue to grow faster than any other industry.

The design tools industry has been doing its part, raising the level of abstraction in the design, modelling and validation flows. Tools have added new functionality and the methodologies have become more integrated over time, so that, for example, synthesis now knows something about place and route and vice versa.

De Geus used part of his keynote to discuss new tools, and new capabilities for existing tools. Some of the tools are a result of the Magma acquisition and represent new capabilities for Synopsys. The company is extending its flow to include the design and analysis of 2.5D and 3D stacked die in an initiative to create a full flow. Yield Explorer is a conduit for data between design and fab to analyze yields.

A partnership with ARM has resulted in a Protocol Analyzer, and virtual prototypes for ARM multicore IP and includes a virtual design kit. Extending verification are new TLM (Guide) verification tools and the TLM Central web site for peer-to-peer interactions for higher-level verification. And finally, Synopsys is releasing SoundWave Audio Subsystem – all the building-block IP needed for a full audio subsystem.

During a press roundtable discussion, de Geus reiterated his belief that differentiation is hard, but just because something is difficult does not make it different. Synopsys has to be careful about encroaching into customers’ spaces and continue to be a supplier and partner rather than a competitor. The company is trying to find niches that appeal to a broad audience, and then to create subsystems that are good enough to provide value while still allowing customization.

De Geus also said that the current focus on leading-edge processes and designs is directly transferrable to people working on previous-generation processes, a topic that also came up at DATE earlier this month. If a designer is not keeping up with the latest tool changes, they are missing out on new capabilities, functions, and performance. Unfortunately, the design team has to freeze its methodology at the start of its project, meaning that the tools are about 18 months out of date by the time the design tapes out. This time frame is equivalent to five or six tool updates.

At the same time, the ability to continue to increase the levels of abstraction means, for most designers, that there are no significant changes to the design flow when moving to finFETs. Abstracting all of the details and embedding structures in libraries keeps design flows constant, except at the cell level and for fine-grain physical design. The tools need to be aware of the layout to avoid introducing new errors, and the layout and extraction processes will become even more computationally intense to address the various lithography and mask/source optimizations.

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