Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
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