EDA Topics

January 27, 2022

Assure diagnostic coverage from RTL to gate level during analysis for functional safety

Generating accurate ASIL metrics early in the functional safety lifecycle, reduces time-to-certification for ISO26262.
January 13, 2022

Siemens’ Sawicki puts priority on scaling in processes, productivity and systems

More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
January 12, 2022
Formal verification for SystemC thumbnail

Formal verification for SystemC/C++ designs

Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
December 15, 2021

Physical verification of package assemblies no longer hinders package adoption

Learn how Calibre 3D enables circuit and layout verification multi-die assemblies so that heterogeneous die processes can co-exist without significant impact to the deck.
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November 12, 2021
Pre-processing and post-processing techniques for verification

How to optimize productivity and accuracy in IC design and verification flows

Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
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November 4, 2021
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How UPMEM ensured effective power delivery for its processor-in-memory design

PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
October 21, 2021
Sherif Hany Mousa is a Principal Technologist in the Calibre Design Solutions division of Siemens EDA, a part of Siemens Digital Industries Software. Sherif previously held positions as a technical marketing engineer, analog quality assurance engineer, and IC design consultant for physical verification and analog/mixed signal applications. He has authored multiple publications and holds multiple patents in the fields of analog layout porting, hotspot detection and correction, and machine learning-assisted verification flows. Sherif is a senior IEEE member who holds an M.Sc. in Electrical and Communication Engineering, and is currently engaged in Ph.D. research, focusing on circuit analysis.

Advanced symmetry verification is a thing of beauty

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
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September 13, 2021
Swathi Rangarajan is a principal product engineer in the Calibre Design Solutions division of Siemens Digital Industries Software, supporting the Calibre RealTime platform. She focuses on in-design sign-off Calibre DRC checking in custom and digital design tools. Before joining Siemens, Swathi was an application engineer focusing on custom and digital design tool suites. Swathi received her BS in electronics and communication engineering from India, and her MS in engineering from San Jose State University

Hit your tapeout schedules with in-design signoff DRC

Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
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September 3, 2021
Silicon Photonics - Verification - featim - sep21

Silicon photonics verification: Progress through adaptation

SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
July 20, 2021
Credit: laborotorio linux

Making sense of cloud EDA

How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
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