EDA Topics

October 3, 2018
Allen Watson of Synopsys

An open-source framework for greater flexibility in machine-learning development

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
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September 20, 2018
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How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
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September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
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August 14, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
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July 23, 2018
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Doc Formal: The budget case for formal verification

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.
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July 17, 2018
Sean Safarpour is the Director of Application Engineering at Synopsys.

Formal fundamentals: what’s hiding behind your constraints

Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
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July 9, 2018
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Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
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June 18, 2018

Formal fault analysis for ISO 26262: Find faults before they find you

How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
June 18, 2018
Andy Ladd is president and CEO of Baum. He has more than 30 years of experience in the electronics industry. Ladd received a Bachelor of Science degree in Computer Engineering from the University of Illinois at Champaign/Urbana, and a Master of Science degree in Engineering from the University of Michigan at Ann Arbor.

Power analysis isn’t just for battery-operated products

Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
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