EDA Topics

February 8, 2024
Ron Press is the technology enablement director of the Tessent product family at Mentor, A Siemens Business. He is a member of the International Test Conference (ITC) Steering Committee, a Golden Core member of the IEEE Computer Society, and a Senior Member of the IEEE.

How AI improves DFT, test and yield

Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
December 4, 2023
US featim

Want to improve your user experience? Adopt a UX maturity model

A deep dive into the adoption, selection and implementation of models that boost productivity and customer loyalty.
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November 30, 2023
BCI-ROM feature

BCI-ROM: a game-changer for electro-thermal design

The Boundary Condition Independent Reduced Order Model (BCI-ROM) provides vital help in addressing growing electro-thermal challenges in SPICE simulation.
October 19, 2023
Neel Natekar is a senior product engineer in the Design to Silicon division of Siemens Digital Industries Software. Prior to joining Siemens, Neel worked as a design engineer focusing on power delivery solutions for custom CPUs. He received a B.Eng. in Electronics and Telecommunications from the University of Mumbai, and an M.S. in Electrical Engineering, Circuits and Microsystems from the University of Michigan.

Simplify and accelerate PV debug using default results data views

Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
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August 8, 2023
Jeff Wilson is a Product Management Director for DFM applications in the Calibre Design solutions organization at Siemens Digital Industries Software. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

Improved power management and faster time to market?

We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
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May 30, 2023
IJTAG standards progress - featured image

Refreshing the IEEE 1687 IJTAG family for today’s designs

Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.
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May 16, 2023
Oasis P39 Semi

Six reasons why you need better cross-platform validation of OASIS layout database generation

You must understand six comparison concerns and their effect on database equivalency. Adopt a solution with an in-depth object-based approach.
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April 24, 2023
cdc-three-steps-featured-image

Three steps to complete CDC verification

CDC sequential reconvergence can be systematically verified without exhaustive manual review by using the circuit model in this methodology.
April 24, 2023
Matthew Welsh, Siemens DIS

Welcome to the part model era

Standards-based digital threads will revolutionize design through part models that deliver trust, traceability and context across components.
February 28, 2023
Dr. Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Previously, he held positions in management, product marketing, technical marketing and engineering.

Shift left to tackle key O-RAN verification challenges

O-RAN compatible Radio Unit (O-RU) and Distributed Unit (O-DU) verification no longer needs to wait until the post-silicon stage.
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