EDA Topics

March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
February 28, 2020
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Make it easier to exercise state machines with SystemVerilog

How the use of declarative, constraint-based descriptions can help you focus command sequences on areas of interest.
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February 20, 2020
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and inventor of its core technology. He has more than 20 years of experience in functional verification automation and is a pioneer in bringing to market the first commercially available solution for Accellera’s Portable Stimulus Standard.

Verifying AI engines

How can we refine our approach functional verification to deal with the increasing number of systems that leverage artificial intelligence.
February 14, 2020
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A better way to debug P2P results

P2P (point-to-point) resistance is fundamental to IC reliability verification. Handle it more efficiently with detailed, automated path layout analysis.
January 30, 2020
clock-domain crossing featim Jan20

Get CDC protocols right with an automated formal-to-simulation flow

A new clock-domain crossing methodology is described and results provided to show how automation delivers greater efficiency.
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January 19, 2020

How to build your GDS to OASIS conversion flow

Master the three prerequisites of format translation and chose the right one from the various translation strategies.
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January 19, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Accelerate your UVM adoption and usage with an IDE

How an integrated design environment can help you overcome complexities within the Universal Verification Methodology and manage the size of the libraries within it.
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December 17, 2019
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System-of-systems validation for automotive design

How Siemens PAVE 360 platform leverages emulation to deliver the exhaustive test required for the incoming generation of autonomous vehicles.
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November 27, 2019

Managing code coverage to achieve verification closure in low-power SoCs

A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.
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November 22, 2019
Raghav Katoch is a product engineer with the Calibre physical verification team at Mentor, a Siemens business.

Improve your LVS debug productivity

A look at ways to improve LVS debug productivity on complex SoCs through more narrowly targeted debug strategies.
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