EDA Topics

October 17, 2022
Round Table Logo

Rising to the verification challenge of open source

Fast emerging options, like RISC-V, could foster massive growth in design but verification still needs commercial tools, a Semicon West panel found.
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October 6, 2022
3D-IC Stack LVS Connectivity

Building confidence and flexibility in 3D-IC system level design

3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
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September 7, 2022
symmetry verification featim

Interactive checks mean faster, more accurate symmetry verification

Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.
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September 7, 2022

NVMe-oF – The future of cloud storage

NVMe over Fabrics (NVMe-oF) extends the memory standard for burgeoning data traffic and the demands of AI and machine learning.
September 6, 2022
Jeff Hancock is a Senior Product Manager in the Embedded Platform Technology Business Unit of Mentor, A Siemens Business. He oversees the Nucleus and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services.

Keeping up with rapid innovation in cockpit domain controllers

Automotive cockpit design is being driven forward by prevailing trends in the wider market.
May 19, 2022
DO-254 CDC FeatIM

Fly the friendly skies with automated CDC verification for DO-254

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.
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May 10, 2022
Coordinate-based checks feature

A quick and easy way to calculate P2P resistance and current density

Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
April 28, 2022
James Paris is a senior product engineer with the Design to Silicon division of Siemens Digital Industries Software, supporting Calibre design interfaces. Prior to joining Siemens, he held roles in analog/mixed-signal physical design implementation and flow development for various IC design companies. James holds a BS in Computer-Aided Design Engineering and an MBA in Marketing.

Layout customization improves productivity in design and verification flows

What are the options and how do you balance overarching CAD requirements and personal preferences?
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April 25, 2022
Wu Yang is the technical project management director for Tessent design-for-test products at Siemens EDA.

Toward usable and scalable DFT for 3D IC design

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
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March 21, 2022
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Executable specifications boost SoC and IP efficiency

Automating executable specifications as they evolve can deliver major efficiencies.
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