EDA Topics

May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
May 3, 2021
Static checks May 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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April 9, 2021
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Spiral in on silicon bugs in six formal steps

The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
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April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
March 2, 2021
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Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs

A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
March 1, 2021
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Machine learning overcomes library challenges at the latest process nodes

From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
December 10, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

e language users deserve IDE support too

With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
December 9, 2020
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Addressing challenges in IC verification configuration

Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
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