EDA Topics

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.

The argument for an integrated approach to SoC verification

A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use