EDA Topics

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

CDC violations are now so complex that it takes a combined block and full SoC level verification strategy to catch and fix all the bugs

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.

A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.