EDA Topics

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.

An in-depth look at the role of FPGA-based prototyping and the validation use cases it offers when integrating complex blocks.

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.

The next boost to verification productivity will come from the integration of multiple strategies and tools.

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.