Floorplanning complex SoCs with multiple levels of physical hierarchy
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
floor planning
A short introduction to IC Compiler II
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
Using optimized design flows to meet PPA goals for SoC processor cores
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
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