February 22, 2016
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
October 31, 2014
A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.
September 18, 2014
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.