Verifying clock domain crossings in UPF-based low-power SoCs
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
EDA Topics
Adding system-level, post-layout electrical analysis to HDAP design and verification
Adoption of high-density advanced packaging (HDAP) needs tools and supports to build designers' confidence in the emerging technology.
8.8 billion miles to verify
How the digital twin can fuel automotive verification flows impossible in the real world.
Reliability verification: It’s all about the baseline
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.
How to improve throughput for gate-level simulation
Innovative methodologies, strategies and tool features help overcome other inefficiencies in complex but necessary simulations.
An open-source framework for greater flexibility in machine-learning development
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
How Starblaze combined simulation and emulation to design SSD controller firmware
This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.
EUV’s arrival demands a new resolution enhancement flow
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Doc Formal: Achieving exhaustive formal verification of packet-based designs
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Managing waivers in reliability verification
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
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