ESL

March 7, 2012

Three essential steps to SoC design and verification

An evolved ESL-to-RTL methodology flow addresses the ‘discipline gaps’ between software and hardware engineering by using three system level-based software-hardware verification steps. The strategy is already available in TSMC’s Reference Flow 12.
February 9, 2012
Dennis Brophy

New SystemC reference simulator open for public comment

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy. Here's what’s new in the proof-of-concept simulator, and how you can participate to refine the Accellera Systems Initiative’s work for standardization.
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January 29, 2012

Transaction level modeling

Transaction-level modeling (TLM) describes a system by using function calls that define a set of transactions over a set of channels.
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January 23, 2012

Seven habits of highly effective virtual prototypes

Virtual prototyping is not a new technique, but the advent of transaction-level modeling and an increased focus on seven key requirements for their effective use means that today's versions are much more broadly applicable and comparatively future proof.
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August 23, 2011

The white heat of technology

We report from National Instruments’ annual user conference, NIWeek 2011, held in a sizzling Austin last month.
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August 23, 2011

The Universal Verification Methodology: ready, set, deploy

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
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June 1, 2011

The new semiconductor ecosystem: wants and needs

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
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February 25, 2011

How to create adaptors between modeling abstraction levels

The article is abstracted from a presentation given at NASCUG by Umesh Sisodia and originally developed by Ashwani Singh of CircuitSutra Technologies on how to create adaptors between various modeling abstraction levels in SystemC.
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December 14, 2010

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture

This paper describes Medea, a NoC-based framework that uses a hybrid shared-memory/message-passing approach. It has been modeled in a fast, cycle-accurate SystemC implementation enabling rapid system exploration while varying several parameters such as the number and type of cores, cache size and policy, and specific NoC features. Also, each SystemC block has its RTL counterpart [...]
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September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
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