August 23, 2011

The white heat of technology

We report from National Instruments’ annual user conference, NIWeek 2011, held in a sizzling Austin last month.
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August 23, 2011

The Universal Verification Methodology: ready, set, deploy

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
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June 1, 2011

The new semiconductor ecosystem: wants and needs

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
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February 25, 2011

How to create adaptors between modeling abstraction levels

The article is abstracted from a presentation given at NASCUG by Umesh Sisodia and originally developed by Ashwani Singh of CircuitSutra Technologies on how to create adaptors between various modeling abstraction levels in SystemC.
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December 14, 2010

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture

This paper describes Medea, a NoC-based framework that uses a hybrid shared-memory/message-passing approach. It has been modeled in a fast, cycle-accurate SystemC implementation enabling rapid system exploration while varying several parameters such as the number and type of cores, cache size and policy, and specific NoC features. Also, each SystemC block has its RTL counterpart [...]
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September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
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June 1, 2010

Winning the power and temperature battle with ESL exploration

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.
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April 14, 2010

SystemC AMS—holistic analog, digital, hardware and software system-level modeling

One year after the publication of a draft, the analog and mixed-signal (AMS) extensions to SystemC AMS will be issued as a standard at the Design Automation and Test in Europe conference in Dresden in March 2010. At this point, SystemC/SystemC AMS will become the first ESL technology to cover continuous time modeling as well [...]
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April 14, 2010

Dresden’s designs on DATE

Europe’s premier EDA conference moves to Silicon Saxony
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December 1, 2009

Overcoming the limitations of data introspection for SystemC

The verification, test and debug of SystemC models can be undertaken at an early stage in the design process. To support these techniques, the SystemC Verification Library uses a concept called data introspection. It lets a library routine extract information from SystemC compound types, or a user-specified composite that is derived from a SystemC type. […]

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