Electronic system level (ESL) design is moving to a new stage in its development, advancing from a proof-of-concept environment to one that is seeing its adoption and deployment at the forefront of design. The article terms this shift ‘ESL 2.0’. The reason for this goes beyond mere marketing hype. Inherent in the transition defined above […]
Since the early 1980s,most of the semiconductor business has been enthralled by the microprocessor, the PC and commodity DRAMs. For all the talk of potential ‘better markets’ and ‘more profitable businesses to be in’, PCs and their brethren came to represent 35- 40% of the industry’s output. They constituted the prime platform for not only […]
Today’s increasingly complex designs typically need to undergo verification at three different levels: block, interconnect and system. There are now well-established strategies for addressing the first two, but the system level, while in many ways the ultimate test, remains the weakest link in the verification process. System verification normally begins only after a prototype board […]
We have entered the era of the multi-processor system-on-chip (MPSoC) but it remains a major frustration that, for a technology that is so imminent and so necessary, there is as yet no real vision out there that goes beyond the parochial. Yes, ‘point’ issues are also being addressed, but we need to define the concept, […]
Increasing system complexity is forcing design teams to avoid errors during the process of system refinement and reduce ambiguities during system implementation to a minimum. On the other hand, the system design approach they choose must enable a project to advance rapidly through all stages of refinement from an algorithmic model to a real system-on-chip […]
When I left the semiconductor industry to become an EDA Analyst, I was struck by two things. The first was the professionalism of the PR firms handling the EDA accounts. They not only did jobs that would be expected of them by silicon vendors, but also performed functions that we would consider part of a […]
Network-on-chip (NoC) could prove to be an effective methodology that addresses interconnect roadblocks to the development of more complex systems-on-chip. However the term covers many approaches, some of which – simple enhancement to existing bus technologies, the costly adaptation of theoretical networking concepts – fall short either in terms of performance or NREs. The article […]
System-level architectural decisions made before any RTL code has been written have a much larger impact on overall system energy than RTL-level, gate-level, or circuit-level tweaks. The Xenergy tool from Tensilica estimates energy for a processor subsystem (processor, caches, local memories) based on the application code that will run on that subsystem. Designers can thus […]
The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]
There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%. The problem is further compounded […]