65nm

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.