How new RTL floorplanning techniques speed physical design
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
physical synthesis
Interconnect resistance
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Eliminating iterations in gigahertz ASIC handoff
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis