April 3, 2024
A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
September 19, 2019
Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
December 2, 2016
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
August 7, 2014
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
June 18, 2014
How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
December 9, 2013
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
May 29, 2013
How to design with finFETs, including the impact on standard cells, IP, SRAM; the effects of fin quantization; extraction and parasitics; AMS issues and more.
September 12, 2012
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
June 1, 2012
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
April 14, 2010
A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]