layout dependent effect (LDE)

May 3, 2021
Static checks May 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
April 15, 2019
Critical Area Analysis Feature - Featured Image

How critical area analysis improves yield

CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
October 8, 2013
Cadence EAD flow

End mixed-signal infinite loops with electrically aware design

Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
October 2, 2013

Catching layout-dependent effects on-the-fly

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
Article  |  Topics: EDA - DFM, IC Implementation  |  Tags: , , , ,   |  Organizations:
April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

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