Addressing challenges in IC verification configuration
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
High-performance computing, processor, and artificial intelligence (AI) chips drive global technological innovation and expansion across industries and consumer markets. Designing these chips is complex and challenging. IC designers must constantly strive to meet ever more strenuous and exacting goals for power, performance, and area (PPA).
The ever-expanding scope and complexity of these goals can only be satisfied through accurate and comprehensive physical and circuit verification. They contribute to a relentless pressure on time-to-market schedules. Even with the extensive use of EDA verification tool suites, it is not surprising that layout verification stages often end up being the most significant time factor on the critical path to tapeout.
Design companies, foundries, and EDA tool suppliers must work closely together to ensure that designers meet their PPA goals and tapeout on time. Foundries lead the way, first by creating rule decks that define the requirements of their manufacturing processes; and second by evaluating the ability of verification tools to compare designs against those requirements to ensure compliance. This design verification ensures taped-out designs can be successfully fabricated. Design companies focus on finding the best EDA tools for each stage in their design flows. Because most companies prefer to use a mix of tools from different EDA suppliers, interoperability across them is critical to supporting a fast, accurate design flow. In support of both foundries and design companies, EDA tool suppliers constantly implement tool innovations focused on improving performance, accuracy, interoperability, automation, and debug capabilities. All the functionality they provide helps the design community optimize the quality and performance of their designs within their tapeout schedules, while also ensuring the foundries can deliver the manufactured chips at a profitable yield.
One key component in physical and circuit verification flows is the setup of the environment used to deploy foundry rule decks in design flows. The right mix of rule decks, inputs, variables, and operating conditions ensures that designers are optimizing the accuracy and performance of their signoff verification flows. Creating a configuration setup manually is time-consuming and error-prone. To increase designer productivity, EDA companies provide interface tools that enable design teams to quickly and accurately set up methodologies that are automated, repeatable solutions integrated into their design and verification tools. By enabling the creation of these run configurations in a consistent, easy-to-use visual environment, these interface tools eliminate multiple time-intensive manual tasks, freeing up more time for designers to focus on meeting design goals and tapeout schedules.
IC verification configuration
There is much more to getting to tapeout than the verification run alone. Engineers must specify and configure the inputs and deploy the appropriate engines within their design flows. They must select and configure run-time variables, debug error results, and communicate with their industry partners. Making all this activity feasible and consistent is the job of the interface tools. For example, the Calibre toolsuite from Mentor, a Siemens business, provides three interfaces that enable designers to manage these tasks easily and efficiently:
- The Calibre Interactive interface is an invocation GUI that allows designers to specify verification configurations and initiate verification runs from within their familiar IC design environment.
- The Calibre RVE results viewer provides an intuitive and easy-to-use graphic user interface (GUI) for reviewing and debugging the error results from Calibre verification jobs, while its interactive HTML report generation enables tools from different EDA suppliers to communicate with each other without exchanging proprietary data.
- The Calibre DESIGNrev chip finishing interface enables designers to quickly and efficiently prepare full-chip design files for tapeout.
Because every verification flow begins with, well, verification, let’s look at how design teams can use the Calibre Interactive interface to set up and initiate runs for physical, circuit, and reliability verification, as well as parasitic extraction.
Managing verification setup
The Calibre Interactive interface presents designers with a GUI they can use to invoke the engines that manage execution of the Calibre verification toolsuite:
- Calibre nmDRC design rule checking (DRC)
- Calibre nmLVS layout vs. schematic (LVS)
- Calibre PERC reliability checking
- Calibre xRC™/xACT parasitic extraction (PEX)
This GUI enables computer-aided design (CAD) engineers and design teams to specify the verification setup in a simple, maintainable, and reproducible way, seamlessly enabling the deployment of foundry rule decks to design flows. By providing an infrastructure that allows engineers to interactively set-up and manage these run configurations, the Calibre Interactive interface eliminates the need to write and maintain code to build these run infrastructures in-house—which any engineer can tell you is very time-consuming.
Streamline foundry deck deployment
One constant challenge for engineers who create verification flows is to provide design teams with a configuration setup that is relevant to the task at hand, as well as simple to use for their process node, design type and stage in the design flow. And the setup should be easy to configure, maintain, and reproduce across multiple invocations. The Calibre Interactive interface provides designers with a consistent, easy-to-use GUI so they can quickly choose the relevant inputs and launch their Calibre verification job.
Because the Calibre toolsuite is independent of design style, design teams can use the Calibre Interactive interface to control a single physical/circuit/reliability verification and parasitic extraction flow for designs containing analog, digital, mixed-signal or radio frequency (RF) components (Figure 1). Setup data and options are encapsulated in runsets—templates that capture the set-up for Calibre verification runs in a single file. Runsets simplify the configuration, maintenance, and reproducibility of setup specifications such as access to correct rule files, run directories, and other required settings.
Using runsets eliminates issues commonly encountered when launching physical/circuit verification or parasitic extraction jobs, such as which input options to specify, selection of the correct path to the rule deck, or where to place output files to avoid overwriting previous results. Designers use the same familiar and easy-to-use GUI to launch all their Calibre jobs, minimizing the chance of errors caused by incorrect specification of inputs. Using a single GUI to create runset files that manage physical and circuit verification runs at both the cell/block and full-chip level also eliminates discrepancies caused by different designers using out-of-sync verification rules as well as the maintenance associated with supporting multiple verification flows. CAD engineers can create runset files for different process nodes and design stages, and easily maintain and enhance them as needed.
Because Calibre Interactive runsets have the same look-and-feel across all design environment integrations (Figure 2), CAD and design engineers have the same user experience, and can use the same runsets across tool integrations to launch Calibre verification and extraction runs with no additional effort or training, even when or if they switch their design environments.
Optimize check selection for DRC runs
One universal requirement for designers, especially at advanced nodes, is to find gross or systemic issues. These can cause an explosion in the DRC error count at various design stages. An efficient way to handle this issue is to create a ‘check recipe’. This contains a subset of checks relevant to the given design stage, and you then run only these checks. For example, when you are designing standard cells or small blocks, running context-based checks such as connectivity and density checks will create many false violations that disappear when these cells or blocks are later placed in higher-level blocks. By eliminating these checks from the runset, designers can save time that would otherwise have been wasted debugging false errors.
The Calibre Interactive interface contains a check recipe editor that enables engineers to easily create recipes and use them across all Calibre nmDRC runs (Figure 3). Because these recipes are automatically saved to runsets, they can be deployed to all designers and sites in the company as part of the standard Calibre Interactive infrastructure. The recipe editor also contains built-in Calibre nmDRC Recon early verification recipes, which automatically select the appropriate checks to run in early design phases. These recipes are based on the Calibre nmDRC rule deck, and run 6-12x faster than a Calibre nmDRC run containing all checks. Users can customize the Calibre nmDRC Recon recipes even further by adding or removing checks using the Calibre Interactive recipe editor.
Customize Calibre verification runs
Using a single GUI to view and control the inputs before launching Calibre verification runs eliminates the need for the designers to remember or refer back to process design kit (PDK) release notes for available runtime variables. This GUI becomes even more useful when designers must move to a new process node or a different foundry, or when a design company has multiple designs in multiple process nodes.
Engineers can write Tcl code to create a customization GUI in the Calibre Interactive infrastructure that designers can use to specify and control the runtime variables for a Calibre run (Figure 4). Controls that designers commonly customize are variable and DEFINE switches, as well as Tcl variables for a Tcl verification format (TVF) rule file.
Built-in Tcl commands enable CAD and design engineers to get and set the Calibre Interactive GUI settings from the customization GUI. They can also specify a primary-secondary relationship for the controls in the customization GUI to manage the visibility of the secondary control on the state of one or more primary controls.
CAD engineers typically want to run proprietary scripts before and after a Calibre run in the design or shell environment, to generate some of the inputs needed for a Calibre verification run. Examples of these scripts include:
- Setting environment variables required for a Calibre nmLVS run, dependent on the design open in the design tool;
- Generating a standard verification rule format (SVRF) variable statement, dependent on the TOP cell; and
- Automatically loading the runset file to use, dependent on whether the Calibre run is a DRC, LVS, PEX or PERC run.
The Calibre Interactive GUI enables designers to run these proprietary scripts using both internal and external triggers (Figure 5). External triggers operate when a designer starts or exits the Calibre Interactive interface from a layout or schematic viewer that supports external triggers. They are written in the API for the supported design environment using the API language (e.g., Tcl/SKILL). Internal triggers operate before and after a Calibre run in the Calibre Interactive interface, and can be saved to a runset. Internal trigger functions run in the Linux shell or a supported design tool.
Many invocation GUIs from EDA suppliers, including the Calibre Interactive interface, play a pivotal role in ensuring that CAD and design engineers can deploy their foundry PDKs to their design flows and launch design or verification runs. However as companies continually move to more advanced nodes, and tapeout schedules become more aggressive, design companies are required to focus more on PPA, limiting the time for physical and circuit verification even further. Furthermore, every chip design company has its own requirements and constraints, so there is no one-size-fits-all verification process. To complete verification tasks quickly, easily, and accurately, design teams must find a way to customize the runs to their specific situation, without needing to become EDA tool developers themselves.
IC run configuration is always going to contain a multitude of options and requirements. Looking at the current Calibre Interactive GUI, there are still quite a few settings through which designers must navigate. Opportunities exist to enable even more streamlined customization and deployment to ensure that designers can quickly select the relevant settings and launch their verification jobs. Considering the number of verification runs designers launch in a tapeout cycle, even modest gains in the efficiency of IC configuration and customization through supporting tools like the Calibre Interactive interface can represent significant gains in productivity.
To find our more about the strategies and features discussed in this article, read this whitepaper: Customize and standardize your IC verification configuration.
About the author
Srinivas Velivala is a principal product manager with the Design to Silicon division of Mentor, a Siemens business, focusing on developing the Calibre RealTime interface and other Calibre integration and interface technologies. Before joining Mentor, he designed high-density SRAM compilers. Srinivas has more than 12 years of design and product marketing experience and holds a B.S. and M.S. in Electrical and Computer Engineering.