Intel’s security architect lays out protection plan
At DAC 2014, Intel’s chief security architect Ernie Brickell described the processor maker’s approach to protecting hardware and software from hacks and attacks.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond
Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore’s law scaling
EDA industry must look to new markets for growth – Rhines
New markets such as hardware cyber security, automotive and embedded software key to EDA industry growth
3D and EDA need to make up for Moore’s Law, says Qualcomm
Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.
Synopsys adds formal, CDC, low-power checks to Verification Compiler
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers’ toolbar
Remember 20nm? Qualcomm does
Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC’s 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
Chipmaking’s future: all of the nodes all of the time
The stall in Moore’s Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible – the idea is familiar but how do you get there?
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.