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Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.

Oberon Microsystems has ported a set of low-overhead cryptographic codes suitable for Apple's HomeKit to the Cortus APS3RP 32bit processor core.

The company's annual 'What to see' list is now available for download and highlights some of EDA's less recognized areas of innovation.

A new dedicated automotive power tester helps cut simulation errors to just 0.5% with more faithful calibration.

Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.

Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.

The latest release of Cadence's Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.