Blog Topics

If you're planning your DAC visit or want to set some Google Alerts for next week, it's time to consult the perennial touchstone.

But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

French start-up and conference debutant joins the drive to ease partitioning for FPGA prototypes

UCIS 1.0 will provide a common format to analyze and compare data from different vendors' tools. Yup, it's a 'Biden' of a deal.

The partnership's 3.1 specification is open for review, with performance enhancements and alignment to Accellera's IP-XACT for metadata

Texas Instruments has put together a tool aimed at users of its MSP430 microcontroller family that will help cut the power consumption of their applications.

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.

The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.

This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.