September 23, 2015
AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?
November 6, 2014
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 28, 2014
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 10, 2014
FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
August 29, 2014
EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
May 14, 2013
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
November 5, 2012
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
August 18, 2012
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
July 11, 2012
Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.