Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
DFT
Toward usable and scalable DFT for 3D IC design
Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
Streaming Scan Network technology delivers ‘no compromise’ DFT for AI designs
A new technique is especially efficient for AI chips with modular, tiled design strategies leveraging multiple instantiations of the same cores.
How to optimize test patterns based on critical area
The world of ATPG just changed with the introduction of a new way to create and choose the most effective test patterns.
Catch the next wave in DFT automation
It is easier than ever to build a flexible, resilient, and end-to-end hierarchical DFT flow with smart automation.
How to gain a competitive edge with advanced DFT
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
International Test Conference celebrates 50 years of advancing test technology
It's the fiftieth International Test Conference this year. How much has been achieved and how much more work is there to do to ensure that we can keep building chips that do what they are supposed to?
AI firsts (and more) at America’s SEMICON
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Achieving more efficient hierarchical DFT for Arm subsystems
Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.
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