DFT

July 3, 2012
Juergen Schloeffel

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
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January 24, 2012

Design for test: a chip-level problem

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
August 23, 2011

Ensuring the reliability of non-volatile memory in SoC designs

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
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August 23, 2011

The testiest place on earth

But in a good way. As ITC moves to Anaheim’s Disneyland in September, we preview the 2011 edition.
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June 2, 2011

Creating a rugged standard for embedded memory

Most memory module standards have not been specified with particular reference to extreme environments where shock and vibration may present significant risk. Rather, designers have had to use a number of workaround techniques, strapping or even directly soldering devices to the board. In addition, the drive toward smaller board sizes is presenting a number of [...]
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June 2, 2011

Strategic considerations for emerging SoC FPGAs

This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
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February 25, 2011

Innovations at ITC 2010

Poster sessions are all too often given Cinderella status at major conferences, but they often contain novel and interesting responses to current technology challenges. This article reviews five poster papers that were released at the 2010 International Test Conference ranging in topic from improved device interfaces for gigahertz test to IP security to the diagnosing [...]
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December 14, 2010

Achieving teraflops performance with 28nm FPGAs

FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
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June 1, 2010

Energy debugging – the next step in MCU software optimization

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.
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April 14, 2010

The new kid on the USBlock: introducing SuperSpeed 3.0

The USB 3.0 specification was approved in 2008 and the first certified products to take advantage of its SuperSpeed (5Gbit/s) were launched at January’s Consumer Electronics Show in Las Vegas. As more support for the standard becomes available, engineers will find themselves considering the specification’s implementation on all types of system projects during the course [...]
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