20nm test demands new design-for-test and diagnostic strategies
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
DFT
When good DFT goes bad: debugging broken scan chains
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
Welcome to IJTAG: a no-risk path to IEEE P1687
Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.
Why cell-aware testing is important
Characterizing standard-cell defect mechanisms helps improve IC testing
Design for test: a chip-level problem
The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
Ensuring the reliability of non-volatile memory in SoC designs
This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
The testiest place on earth
But in a good way. As ITC moves to Anaheim’s Disneyland in September, we preview the 2011 edition.
Creating a rugged standard for embedded memory
Most memory module standards have not been specified with particular reference to extreme environments where shock and vibration may present significant risk. Rather, designers have had to use a number of workaround techniques, strapping or even directly soldering devices to the board. In addition, the drive toward smaller board sizes is presenting a number of [...]
Strategic considerations for emerging SoC FPGAs
This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
Innovations at ITC 2010
Poster sessions are all too often given Cinderella status at major conferences, but they often contain novel and interesting responses to current technology challenges. This article reviews five poster papers that were released at the 2010 International Test Conference ranging in topic from improved device interfaces for gigahertz test to IP security to the diagnosing [...]