March 1, 2008

High quality scan test with minimal pins

Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]

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December 1, 2007

Implementing DDR3 DIMMs with modern FPGAs

While DDR3 SDRAM offers speed and low-power benefits, the fly-by termination topology defined by the JEDEC specification for DDR3 SDRAM DIMMs creates interesting challenges for FPGAs. The JEDEC topology significantly reduces the simultaneous switching noise that plagues high-frequency parallel interfaces, but also introduces the need for read and write leveling to compensate for the deliberate […]

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September 1, 2007

What to look for when using an external PCB design center

The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]

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June 1, 2007

New breed of SPYDER discovered

Freescale Semiconductor manufactures some of the industry’s most widely used microcontrollers. The article describes the functionality behind the new Background Debug Module that has been developed for its 8 and 16bit MCUs. The BDM provides all that is needed to write, compile, download, in-circuit emulate and debug code, when deployed in conjunction with the well-known […]

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March 1, 2007

Re-evaluating the flow for package-aware chip design

Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]

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December 1, 2006

Left shifting DFM analysis into the PCB design flow

What do we mean by a ‘left shift’ in design for manufacturing (DFM) analysis? Think of it as moving the DFM analysis from a tool run by the manufacturer into an integrated solution within the printed circuit board (PCB) design system. It is a major advance in the design of PCBs, allowing users to ultimately […]

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December 1, 2006

Silicon carrier for computer systems

Applications ranging from gaming to digital media to data analytics continue to grow more complex and constantly demand increasing computing power from computer systems. Historic growth in microprocessor performance has primarily been responsible for assuring a steady growth in the computing power of computer systems. Traditionally, this growing performance has been sustained by scaling down […]

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September 1, 2006

Embedded non-volatile configurable program storage

Processor program storage today Most of the microcontrollers currently on the market store program code in one of three ways: in ROM on the same chip as the MCU; in embedded flash memory on the same chip as the MCU; or as external flash memory whose contents are downloaded to the MCU. Each of these […]

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June 1, 2006

Accelerating the move from prototype to production with a robust design flow

When migrating from FPGA prototype to ASIC, engineers need to interface with multiple silicon and software vendors. Designing with FPGAs often requires the use of several software platforms, including front-end synthesis tools, FPGA software development tools, and verification and timing analysis tools. Migrating to an ASIC platform involves using a parallel design flow with different […]

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March 1, 2006

The future of high-performance computing: direct low-latency peripheral-to-CPU connections

For peripheral card and system manufacturers, delivering low-latency high-performance computing solutions at affordable prices has been an insurmountable barrier. Although processor speeds and bandwidth have taken quantum leaps over the last decade, the last few inches between the adapter slot and system CPU represent a bottleneck that restricts the development of cost-effective high-performance computing solutions. […]

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