December 1, 2009

Silicon test moves up the food chain

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

September 1, 2009

Pushing USB 2.0 to the limit

USB offers many advantages for use on embedded systems, although software developers remain concerned about the additional complexity it can bring to an application. For example, software drivers for SPI, RS-232 and other traditional serial protocols typically involve little more than read and write routines, while USB software drivers can span thousands of lines, incorporating […]

Article  |  Tags:
September 1, 2009

Ensuring reliability through design separation

System designs have traditionally achieved reliability through redundancy, even though this inevitably increases component count, logic size, system power and cost. The article describes the design separation feature in Altera software that seeks to address these as well as today’s conflicting needs for low power, small size and high functionality while maintaining high reliability and […]

Article  |  Tags: ,
June 1, 2009

Antenna design considerations

An overview of antenna design considerations is presented. These considerations include system requirements, antenna selection, antenna placement, antenna element design/simulation and antenna measurements. A center-fed dipole antenna is presented as a design/simulation example. A measurement discussion includes reflection parameter measurements and directive gain measurements. Antenna requirements Gain and communication range With the advent of prolific […]

Article  |  Tags:
December 1, 2008

IP hardens up again

Richard Goering System-on-chip designers who work with third-party silicon intellectual property (IP) will see some significant changes at 32nm and below. Physical IP will be highly optimized to specific processes, following intense collaborations between large IP providers and foundries. Processor IP may become less synthesizable and make more use of hard macros. On the plus […]

Article  |  Tags:
December 1, 2008

OCP performance monitoring with programmable instruments

The process of proving the system is working and performing optimally, under all application and environmental conditions, has become too inefficient and difficult for existing methodologies. Traditional methods for addressing post-silicon requirements have reached the point of diminishing returns. What was once an exercise of designing, implementing and verifying 25,000 to 50,000 gates of instrumentation […]

June 1, 2008

Implementing an intelligent solar tracking control system on an FPGA

Given present-day demands for environmentally friendly, renewable energy sources, solar energy is becoming increasingly attractive. However, while solar energy is free, non-polluting and, in practical terms, inexhaustible, there remain significant inefficiencies in capturing it. For example, solar panels are traditionally fixed and in this configuration cannot capture the maximum amount of sunlight during changing weather […]

Article  |  Tags:
March 1, 2008

High quality scan test with minimal pins

Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]

Article  |  Tags:
December 1, 2007

Implementing DDR3 DIMMs with modern FPGAs

While DDR3 SDRAM offers speed and low-power benefits, the fly-by termination topology defined by the JEDEC specification for DDR3 SDRAM DIMMs creates interesting challenges for FPGAs. The JEDEC topology significantly reduces the simultaneous switching noise that plagues high-frequency parallel interfaces, but also introduces the need for read and write leveling to compensate for the deliberate […]

Article  |  Tags:
September 1, 2007

What to look for when using an external PCB design center

The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]

Article  |  Tags:


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors