EDA Topics

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?

This part illustrates the technique using examples addressing memory corruption, multicore systems and cache coherency with particular reference to watchpoints.

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.

Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.