Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
IC Implementation
How HLS is giving shape to glasses-free 3DTV
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
The Wally Rhines interview – Part One: Mentor as a Siemens business
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
DVCon China launches this April in Shanghai
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
The SSD memory revolution
Richard Pugh looks at how innovations highlighted during the recent International Memory Workshop are driving the solid state drive (SSD) market.
A new path for analog design constraints verification
Traditional techniques are being challenged by shortening design cycles and the effects of later process nodes.
Hierarchical signoff of SoC designs at advanced process nodes
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
Six ways to exploit the advantages of finFETs
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Wally Rhines separates the signal from the noise
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
How place and route is adapting to challenges below 10nm
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.