IC Implementation

September 19, 2019
Hossam Sarhan, Mentor, a Siemens business

Today’s analog/RF designs need interconnect inductance extraction

Parasitic extraction has to take more account of inductive effects as operating frequencies rise and feature sizes shrink in complex SoCs.
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September 13, 2019
John Blyler is a Consulting Editor of Tech Design Forum and the Editor-in-Chief of Interference Technology. He spent the first half of his career as a hardware-system systems engineer and program managerand the second half as a technology journalist, science writer and educator. John is an affiliate professor of systems engineering at Portland State University and lecturer for UC-Irvine’s online IoT program.

AI firsts (and more) at America’s SEMICON

SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
September 10, 2019
Adnan Hamid is co-founder and CEO of Breker Verification Systems, and the inventor of its core technology. He has more than 20 years of experience in functional verification automation. He received his Bachelor of Science degree in Electrical Engineering and Computer Science from Princeton University, and an MBA from the University of Texas at Austin.

Using portable stimulus for automotive random error analysis

The Portable Stimulus Standard helps overcome many of the verification challenges inherent in the strict requirements of ISO 26262.
September 9, 2019

Getting better results faster with a unified RTL-to-GDSII product

Complex SoCs need systemic optimisation to achieve best time to results, enabled by the use of a unified RTL-to-GDSII flow underpinned by a unified data model.
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July 23, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Correct design and verification coding errors as you type

An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.
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June 11, 2019
Dennis Joseph is a technical marketing engineer supporting Calibre interfaces in the Design-to-Silicon division of Mentor, a Siemens business. His primary focus is the support and enhancement of the Calibre DESIGNrev layout viewer. Dennis received an M.S. in Electrical and Computer Engineering from the University of Florida.

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.
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May 15, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
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April 2, 2019

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.
March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
January 28, 2019

Emulation for AI: Part Two

The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.

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