IC Implementation

June 21, 2021
LEF abstract vs GDS

Out-of-sync data issues in parallel design flows need automated design integrity checks

Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
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May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
April 29, 2021

DVCon Europe best paper assesses clock design

The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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April 6, 2021

The path to full functional monitoring

Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
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June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
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May 26, 2020
cloud computing efficiencies with calibre for physical verification

How cloud computing is now delivering efficiencies for IC design

A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
April 14, 2020
Power ground check featim

How automated power/ground short checks slash time during implementation

Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
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March 30, 2020
Featured Image ESD feature

Automate P2P resistance checking for better, faster ESD protection

ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
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