Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
A Mentor-Microsoft-AMD pathfinder demonstrates the potential benefits of cloud-based physical verification.
Early detection using design integrity checks during implementation from abstract LEF/DEF inputs can deliver major efficiencies.
ESD has always been a major issue but with increasing densities and growing die sizes it is becoming a higher order concern. Automation and vizualization can help manage the task.
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