Use machine learning and visualization to accelerate Liberty file verification
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Verification
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
Spiral in on silicon bugs in six formal steps
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
The path to full functional monitoring
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Machine learning overcomes library challenges at the latest process nodes
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
e language users deserve IDE support too
With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
Addressing challenges in IC verification configuration
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
Resolving IP cell-name conflicts peacefully
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.