Using on-demand rule checks during place-and-route boosts efficiency and design quality.
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
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