November 12, 2021
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
November 4, 2021
PIM memory boosts efficiency by operating on data without moving it to the CPU but realizing this type of novel technology posed power integration and planning challenges.
October 21, 2021
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
September 3, 2021
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
June 25, 2021
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
June 21, 2021
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
May 31, 2021
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
May 3, 2021
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
April 9, 2021
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
April 6, 2021
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.