Machine learning overcomes library challenges at the latest process nodes
From 16nm, new complexities hinder .lib file characterization and verification but machine learning now offers an efficient way of managing them.
Verification
e language users deserve IDE support too
With features that keep it in current use such as aspect-oriented programming, the e language can leverage integrated design environments. Learn how.
Addressing challenges in IC verification configuration
Invocation GUIs play an important role in delivering efficient verification runs. Learn how to take advantage of the features within Calibre Interactive.
Resolving IP cell-name conflicts peacefully
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
Extract benefit from the automated refactoring of VHDL code
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
P&R filler cell insertion slowing you down? Replace it
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Everything you ever wanted to know about RISC-V architectural formal verification
But you were NOT afraid to ask.... It's time for some answers.
Creating a new paradigm for circuit verification
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
EDA innovation is the foundation of progress
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
How IDEs enable the ‘shift left’ for VHDL
Learn how an IDE offers on-the-fly, auto-correct and informed analysis of VHDL code to speed project quality and delivery.
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