Symmetry verification for analog and custom IC needs to evolve beyond current time-consuming and hard-to-use techniques.
Electrical matching primarily translates to geometrical symmetry in the physical layout making symmetry verification increasingly important. It has a significant impact on the performance and reliability of many types of design, including analog, micro-electro-mechanical (MEMS), and image sensors (Figure 1).
Current symmetry verification approaches tend to be difficult to use, time-consuming, or both. Some involve performing manual measurements with a ruler to validate the symmetry in designs. Some require complex rule checks which assume considerable experience. Some designers perform parasitic extraction runs to compare the values and validate the symmetry, while others implement ‘correct by construction’ design practices that can be risky because they rely on the consistent application of good design practice and error-free placements.
A further limitation common to all these techniques is the lack of guidance during the debugging process, making root cause identification and correction of symmetry errors a challenge in and of itself.
With design complexity on the rise as the demand for accurate and precise high-performance ICs grows, designers need a symmetry verification solution that not only simplifies the process, but also provides the guidance they need to debug errors and implement the optimum fixes. In addition, the ability to perform symmetry verification inside the design environment at any point during layout design can give designers the opportunity to find and eliminate symmetry errors earlier.
IC design symmetry
IC design symmetry requirements are normally considered from two perspectives. One-dimensional (1D) symmetry is symmetry between devices as related to either the horizontal or vertical (x or y) axis, while two-dimensional (2D) symmetry (also known as common centroid symmetry) means devices or combinations of devices must be symmetrical to each other with respect to their center of gravity.
The Calibre nmPlatform from Siemens Digital Industries Software allows designers to perform the checking needed to verify both types of symmetry. The Calibre interactive symmetry solution leverages the Calibre RealTime interface. Designers can interactively select an area of interest for symmetry validation. When symmetry violations are found, generated error markers help designers identify the root cause of the violation and implement the appropriate fix. To validate that applied fixes are DRC-clean, designers can upload the Calibre signoff DRC rule deck to run in parallel with the symmetry checking.
Symmetry checking and error fixing
Using the Calibre interactive symmetry solution for the differential-pair op-amp device in Figure 3, three symmetry violations are identified around the y-axis.
Once the symmetry error is identified, the next step is to determine the root cause, so the best fix can be applied. This is not always evident in a visual inspection of the layout, so providing designers with error details can help guide them to the correct solution. For example, because the Calibre interactive symmetry checking flow also provides error hints, the root cause of the third error (a 2nm difference in polygon lengths) from the earlier example can be made readily apparent to designers (Figure 4).
Once the root cause of the symmetry error is determined, designers must decide the best way to correct the error. In this example, when determining the optimum fix for the third violation, designers must decide whether to make the polygon at the left shorter, or make the right polygon longer. Because designers can load the Calibre sign-off DRC rule deck and run it in parallel with symmetry checking, they can quickly validate whether or not a proposed fix returns DRC-clean results.
Fixing the violation by making the polygon on the right shorter by 2nm results in a DRC violation of the minimum spacing requirement between the metal layer and the active layer below it (figure 5). However, elongating the polygon on the left by 2nm does not create any DRC violations, indicating to the designers that this fix is the correct solution.
The traditional design symmetry verification methods used to achieve a symmetrical layout today inadequate and no longer practical. New automated technology provides the fast, accurate, interactive symmetry verification needed to ensure today’s complex analog designs will deliver the intended performance
Invoking symmetry verification during layout design and on design placements provides the necessary checking when and where designers need it most. Leveraging Calibre symmetry checking in conjunction with Calibre RealTime interactive checking functionality is the type of verification evolution needed to tackle today’s complex devices and symmetry requirements. Fast, accurate, interactive symmetry verification enables design companies to quickly and easily check symmetry earlier in the design flow, and resolve symmetry violations while ensuring a DRC-clean layout.
More information is available in our technical paper: Interactive symmetry checking provides faster, easier symmetry verification for analog and custom IC designs
About the author
Sara Khalaf is an advanced product engineer in the Calibre Design group at Siemens Digital Industries Software, currently working on advanced physical verification technology. Sara received her Bachelor of Science degree in electrical, electronics and communications engineering from Ain Shams University in Cairo.