Expert Insights - EDA

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?

Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.

Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.

Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.

3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.