Jack Erickson |  November 1, 2013
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Piyush Sancheti |  October 16, 2013
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
Axel Scherer |  October 11, 2013
Verify registers without writing code for specific bus interfaces or speed up the loading of configuration registers using the UVM Register Layer. Videos show you how.
Adnan Hamid |  October 7, 2013
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
Steve Smith |  August 12, 2013
3D-IC design is ready for take-off, following several years of intense collaboration to develop the necessary tools, methodologies and flows
Dan Benua |  July 25, 2013
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
Graham Bell |  July 3, 2013
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Graham Bell |  May 14, 2013
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
Graham Bell |  May 7, 2013
Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Mick Posner, Synopsys |  April 24, 2013
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.